amd表示，它正在向元平台提供可编程的无线电SOCS，作为计划的一部分，以降低建立庞大的无线网络的成本，这些无线网络可以处理元数据中的大量数据。
The Santa Clara, California-based chip maker is offering its Xilinx-designed Zynq UltraScale RFSoC to Meta’s Evenstar program, whichpromotes the new Open RAN technology用于建筑4G和5G基站。
amd's partnership with Meta follows its$49 billion acquisition of Xilinx，在2月关闭。
All About that Base Station
A base station—also called the radio access network (RAN)—is a set of hardware modules that are usually mounted on poles or buildings and connect phones or other devices to a wireless network. The RAN includes a radio unit (RU) that contains radio-frequency (RF) transceivers and other ICs to convert and amplify RF signals. The radio unit is generally located close to or integrated directly into the antennas on a base station.
One of the other key components of a base station is the distributed unit (DU), which houses the baseband processor that runs L1 (or PHY) functions of the RAN protocol stack—or shares the load with the RU. The final component is the central unit (CU), which runs inside the carrier's cloud data centers and controls several of the DUs.
根据行业分析师的说法，当今的基站充满了专有界面，因此电信公司被迫在预先集成的硬件和软件捆绑包中从单个供应商那里购买所有组件。
Open RAN允许电信公司与基站的“最好的”硬件和软件混合，而不是从爱立信，华为技术，诺基亚或其他供应商那里购买所有东西。专家警告我们已经过去了从建造基站的完全开放的模型中，但是公开式标准可以使电信公司更加灵活性，并使硬件的定价更具竞争力。
Open RAN allows for flexible partitioning network functions—a concept called disaggregated RAN. AMD said the Zynq RFSoC gives telcos the flexibility to divide baseband processing between the radio and DUs.
适应能力的SOC，硬IP
The RU houses a range of components, including the RF transceiver and digital front end (DFE), which is the building block that AMD is targeting with the UltraScale RFSoC family. The DFE is one of the more critical stages in the base station. It serves as a bridge between the RF transceiver and RF chips to the baseband modem on the other side used to handle the PHY (or L1) signal-processing jobs in the radio.
The DFE can reconfigure the channels in the radio in real-time and carry out pre-processing on radio signals from the base station’s antennas, then clarify them before sending them to the baseband processor in the DU.
With its heterogeneous architecture, the UltraScale RFSoC can serve as a complete software-defined radio that can meet a range of requirements for 4G and 5G networks based on millimeter-wave and sub-6-GHz bands.
AMD称UltraScale RFSoC的组合hardened logic for RF functions while leaving a degree of programmable logic—the same type of logic at the heart of Xilinx's FPGAs—so that its customers can differentiate themselves from other telecom firms.
由于能够在单个无线电中同时在4G LTE和5G模式下运行，因此芯片具有宽带RF收发器，带有八个发射器，八个接收通道，最多400 MHz瞬时带宽（IBW）。
Xilinx RFSOC核心的硬件加速器可以执行数字上转换（DUC）和下调（DDC），以将基带信号向上或向上移动到不同的频率。在支撑7.125 GHz的直接RF带宽内，数字到ANALOG（DACS）和模数转换器（ADC）。硬化的逻辑可以处理其他杂务，例如Crest-Factor降低（CFR），以减少无线电传输中的噪声。
最后，Xilinx-Made RFSOC中的信号处理单元提供重新采样和其他无线电功能。
Open RAN's Future
5G radios require high-end chips that not only meet bandwidth, power, and cost efficiencies for widespread deployment in the field, but they also must have the flexibility to fit new 5G standards such as Open RAN.
Integrating everything on a single compact chip lessens the hardware's power and heat dissipation. The use of hardened IP helps keep costs in check, while programmable logic leaves the door open for design flexibility.
宽的瞬时带宽使其能够为基站中每个天线提供多达八个载体的载体聚集（CA）。同一无线电内的更多数据管道有助于降低系统级别的成本。
There is also a hardware accelerator for digital predistortion (DPD), which is widely used to increase the linearity of RF power amplifiers. This is a soft-core processor that customers can adapt to their specific requirements, AMD said.
RFSOC可以与各种节能功率放大器配对，包括高级宽带GAN功率放大器，可帮助提高4G LTE和5G RANS的功率效率和密度。用作毫米波中间频率（如果）收发器，则提供多达1,600 MHz的带宽。
The AMD-Meta tie-up builds on efforts by other telecom and technology firms that are backing Open RAN.
Open RAN is projected to account for up to 15% of the total market for RAN infrastructure by 2026, according to market research firm Dell’Oro Group.
