Spring in Paris with RISC-V Week

This article is part of theTechXchange:RISC-V: The Instruction-Set Alternative.

RISC-V has moved rapidly from an academic exercise to an ecosystem that includes hardware from major silicon vendors with support from all of the top software vendors. You can program RISC-V processors using languages ranging from C and Java to Rust and Ada. Microchip even has hard-core RISC-V processorsembedded in its FPGA.

Electronic Designwill be hostingExpanding the RISC-V Ecosystemevent onEngineering Academyin September, but if you're in Paris this May, you can take in theRISC-V Weekhosted byRISC-V International. Travel for me is a bit limited, so I’ll have to contend with a remote view of their keynotes and presentations.

In the meantime, you can take a look at the2021 RISC-V Summit, which was a hybrid event as well. Below I’ve chosen a few of the videos to highlight here, but you also can search through the fullRISC-V Summit YouTube playlist. In addition, check out avideo intro to RISC-Vand our11 Myths About the RISC-V ISAarticle to get more acquainted with the idea of RISC-V.

Links

• Engineering Academy
• Expanding the RISC-V Ecosystem
• RISC-V International
• RISC-V Week
• 2021 RISC-V Summit (YouTube)

Selected Sessions from the 2021 RISC-V Summit

Implementing Functionally-safe RISC-V IP for Automotive and Safety Critical Applications

Bringing RISC-V to Life: Building our Software Ecosystem

Formal Verification of RISC-V Cores

Still want more? Check out the fullRISC-V Summit 20201 YouTube playlist.