VME is one of the oldest military/commercial-off-the-shelf (MIL/COTS) buses that still has regular design wins. Its parallel backplane bus was the fastest around at one time. The VME320 standard released in 1997 runs at 320 Mbytes/s, though high-speed serial interfaces like Serial RapidIO and Gigabit Ethernet have superceded the parallel bus.
VITA, the standards group that manages VME technology, started with VME (VITA 1.0). VITA 1.5 defines VME320, or VME 2eSST. The high-speed serial platforms includeVPX(Table 1)那VXS（表2）那andXMC（表3）。VPX和VXS是VME等板标准，并使用3U和6U形式因子。XMC是一种使用高速串行接口的夹层卡标准。它是PCI夹层卡（PMC）的替代方案，WHCH使用并行PCI接口。
VME和PMC与其PCI总线相对稳定，易于抗衡。高速串行接口很好地定义，但可用的选项数量可以铭记。该列表包括串行接口，如串行Rapidio，Infiniband，PCI Express，千兆以太网，10-Gbit以太网，Aurora，HyperTransport和Xaui。虽然这些接口都是点对点连接，但它们通常使用集线器或交换机。
In addition, the reduction of pins needed to deliver comparable throughput on a high-speed serial interface is significantly lower than a parallel interface like VME or PCI. This allows many boards and platforms to handle multiple connections. A single connection allows a star configuration while dual connections support adual-star setup（图。1）那providing redundancy.
A full mesh requires more connections but provides maximum bandwidth. A dual mesh offers redundancy but is a very complex backplane. Even tree or inverted-tree architectures and asymmetrical designs are options that may be more suitable to some applications. For example, a radar processing system might work best with an inverted tree where many inputs are reduced to a single result, with each level of the tree handing off a smaller processed subset of data to the next level.
The options get even more complex when mixing interconnects. This complexity is compounded by the more advancedMultiGig connectors（图2）与VXS和VPX高速串行接口一起使用，如来自Tyco Electronics的VX，其实际上是多个晶片尺寸电路板本身。这些互连在VxS和VPX板上使用，如柯蒂斯赖特控制嵌入式计算器6U VPX CHAMP-AV6（图3）with four Freescale dual-core microprocessors with built-in Serial RapidIO connections.
Add to all this the ability to mix and match high-speed serial interfaces, typically Ethernet with another interface, and it is easy to see how the number of options grows significantly. Designers employing VXS and VPX often require custom backplanes, taking advantage of the backplane I/O connectors available on the 3U and 6U boards and further adding to the chaos. Attaining a level of compatibility between vendors was more than a challenge. OpenVPX looks to bring a little order to the chaotic number of options.
分析标准
以前称为OpenVPX，Vita 65是一种设计的系统级规格，所以通过分析来自Vita的有用的可用标准的有用子集，可以互相播放(see “VPX Moves Forward With OpenVPX And Additional VITA Specs”)。System designers can then start with a profile instead of a lower-level form factor and interconnect level.
VITA 65 came about through cooperation from board vendors such as Mercury Computer Systems, Curtiss-Wright Controls Embedded Computing, GE, and Tek Microsystems as well as customers like Boeing so designs would not be so unique that second sourcing and upgrades would be out of the question. This was often the case where designs could utilize the host of options, not to mention the customization of the I/O connections.
Some of the considerations that went into VITA 65 include backplane architectures and development chassis interconnect topologies, module-level pin designations and protocol definitions, power and system signals, and interoperability compliance issues. The specification also defines various sizes of pipes used for the serial interfaces as well as multiple logical planes for utility, management, control, and data.
Planes define logical and physical interconnets. Pipe definitions include an Ultra Thin Pipe (UTP), a Thin Pipe (TP), a Fat Pipe (FP), a Double Fat Pipe (DFP), a Quad Fat Pipe (QFP), and an Octal Fat Pipe (OFP). This matches well with most high-speed serial interfaces. Interface speeds up to 6.25 Gbits/s per signal pair are supported.
Vita 65采取务实的设计方法。它选择某些选项，可能以牺牲他人为代价，以定义OpenVPX系统如何工作。这应该保证，每个OpenVPX板都将插入OpenVPX背板和工作。
OpenVPX变成了一个广泛的库珀ative effort. It did not start out that way, and there were a few heated discussions along the way. A few non-disclosure agreements (NDAs) and possibly a few arrows were exchanged. The resulting OpenVPX Working Group, which has since dissolved, and standard are better for the effort that is now under VITA.
该标准基于Vita 46 / VPX和Vita 48 / Redi规范，增加了与后转换模块（RTMS）的空气冷却互操作性等方面。这使供应商能够设计与竞争对手可互操作的板。自定义仍然可用，并将区分平台。
Designers can now select from a set of limited parameters such as form factor (3U or 6U), interconnect topology, and number of slots in the backplane. For example, Elma Bustronic’s seven-slotOpenVPX Hybrid backplane(Fig. 4)有五个VPX套接字使用每个电路板的完整网格互连，每个电路板有四个串行接口。
这消除了对交换机的需求。背板还有一对VME / 64X插槽，VME总线路由到VPX连接器。背板引用BKP6-DIS05-11.2.16-1简介。当系统使用的背板和电路板符合Vita 65时，汇编和部署现在显着更容易。
基本配置文件允许设计人员和供应商使用新的兼容硬件，但基本集只是起点。虽然我们的需要，但随着新的架构组合变得更受欢迎，他们不会有一阵新设计。
Two of the new VITA specifications that will have an impact are VITA 66 (Fiber Optic Interconnect) and VITA 67 (coax Analog/RF Interconnect). Fiber and coax connections are common on the front panel. More connections are likely to move to the rear, though, as these standards come into play on the boards and backplanes. VITA 65 support will be critical here.
“OpenVPX: It’s all about the backplane,” says Ray Alderman, VITA executive director. In one sense, VITA 65 has brought back the commonality that VME had delivered in the past.
PARALLEL BACKPLANE IS HERE TO STAY
军事市场与消费者和商业市场不同，在数月或数年内测量技术营业额。军事应用数十年来衡量。这是新设计中的平行总线基于总线解决方案，如VME，CompactPCI，甚至PC / 104的一个原因。这些特定规定通常针对大的替代和升级市场。
VXS尝试将全高速串行背板（如VME的并行接口）桥接全高速串行背板之间的间隙。替代和升级市场中的挑战是底板是否可以改变。如果不是，则VXS板仍然工作，但它们的串行接口被浪费了。否则，设计开辟了一个选择世界。
