锁相环（PLL）是将电压控制振荡器（VCO）和相位检测器组合的反馈系统，使得振荡器信号跟踪具有正确频率和相位的施加的频率或相位调制信号。当需要从固定的低频信号或需要快速变化时，需要产生稳定的较高输出频率时使用PLL。典型用例是在无线电通信链路中以及测试和测量设备中的频率合成，包括矢量网络分析仪（VNA）。
图1shows a block diagram of a PLL-based frequency synthesizer. The VCO generates the output signal. It’s maintained at the setpoint frequency by the PLL and locked to the reference frequency, and the reference frequency is typically supplied by a very accurate quartz oscillator. A frequency divider is provided in the feedback path of the PLL circuit in front of the phase detector to reduce the VCO frequency by an adjustable factor.
VCO包含可调节调谐元件，例如变容二极管，其具有根据输入电压而改变的电容。因此，PLL电路是VCO的一种反馈控制系统。
VCO所需的输入或控制电压通常高于PLL电路可用的电源电压。电源电压通常为3.3或5V，而VCO可能需要超过20V的电压，这取决于所需的频率。为了产生更广泛的频率，可以使用具有更宽调谐范围的VCO。在GigaHertz范围内支持VCO的简化电路示例图2.。
DCYS100200-12来自Synergy Microwave Corporation, for instance, can be used as the VCO. It pumps out a frequency of 2 GHz at 28 V (VTUNE), as can be seen in the graph in图3.。
产生高电压
There are several possibilities for generating the high control voltage. One is using an active loop filter, which essentially consists of a high-speed amplifier and a low-pass filter that shapes the output pulses from the phase detector (CP出去）进入干净的直流电压。或者，具有集成电荷泵的PLL频率合成器，例如ADF4150HV模拟Devices（它不需要额外的主动循环滤波器，可以使用。
Even though both solutions require a high-voltage supply, the number of components can be reduced with the ADF4150HV. Distortion and phase noise caused by the active filter amplifier can also be ousted. Furthermore, the ADF4150HV can be used in fractional-N or integer-N PLL frequency synthesizers. Thus, it’s possible to divide the VCO frequency by 1, 2, 4, 8, or 16 to achieve output frequencies down to a minimum of 31.25 MHz.
ADF4150HV集成电荷泵所需的高电压可以通过ADP1613 DC-DC转换器产生，而不会影响PLL的性能。用作开关调节器，ADP1613具有集成的功率晶体管，实现高达20 V的输出电压。通过使用额外的外部部件，尤其是通过外部功率晶体管，还可以实现更高的输出电压。
The switching frequency of the ADP1613 can be adjusted from 650 kHz to 1.3 MHz, which leads to a better transient response and simple noise filtering. In general, using a switching frequency of more than 1 MHz is recommended so that switching noise can be reduced by the PLL filter.
使用集成的RF分频器时，带ADF4150HV的PLL频率合成器提供超字母PLL功能。该部分还涵盖62.5 MHz至2 GHz的频率。利用相同的PLL设计，可以为系统中的多个不同的硬件平台生成不同的频率。但是，如果您正在使用各种类型的VCO，请将相应的循环过滤器结合到设计中有意义。这样，您可以确保锁相环函数可靠地运行。
通过其相对较宽的输出频率范围和更高的输出功率，ADF4150HV的每个RF输出也需要小过滤器结构。与50Ω电阻并联的27-NH电感器可用于高达3 GHz的频率。电阻器提供定义的输出阻抗。较低的电感会导致频带扩展到较低的范围。
The PLL frequency synthesis simulation tool ADIsimPLL also supports the development of HF functional blocks and modeled high-frequency signal chains. It gives designers the ability to simulate the important nonlinear effects that could impact PLL performance; for instance, undesired spurs from the frequency-synthesis process (spurious frequencies).
大的频率范围(集成解决方案that is, for PLLs, filters, and VCOs) in one housing are also available. But these solutions can lead to undesired coupling due to how close the different parts are to one another. A discrete design and the resulting physical separation minimize this risk.
托马斯品牌是一个现场应用工程师模拟Devices。
References
“Voltage Controlled Oscillator Surface-Mount Model: DCYS100200-12。“Synergy Microwave Corporation，2014年10月。
“电路笔记CN-0228：单电源功率A 28 V，高压锁相循环（PLL）合成器。“模拟Devices, June 2014.
